Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produces devices with 250 nm, 180 nm, and 65 nm feature sizes, and new equipment is being developed and implemented to make devices with even smaller geometries. The decreasing feature sizes result in structural features on the device having decreased spatial dimensions. The reduced dimensions, in turn, require the use of conductive materials having a very low resistivity and insulation materials having a very low dielectric constant.
Low dielectric constant films are particularly desirable for premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metalization, to prevent cross-talk between the different levels of metalization, and to reduce device power consumption. Undoped silicon oxide films deposited using early CVD techniques typically had a dielectric constant (k) in the range of 4.0 to 4.2. In contrast, various carbon-based dielectric layers that are now commonly used in the semiconductor industry have dielectric constants below 3.0. Many of these carbon-based layers are relatively unstable when initially deposited and are subsequently cured in an oxygen environment and/or annealed to increase the films stability.